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HM 9270C/D DTMF RECEIVER
General Description
The HM 9270C/D is a complete DTMF receiver integrating both the bandsplit filter and digital decoder functions. The filter section uses switched capacitor techniques for high- and low-group filters and dial-tone rejection. Digital counting techniques are employed in the decoder to detect and decode all 16 DTMF tonepairs into a 4-bit code. External component count is minimized by on-chip provision of a differential input amplifier, clock-oscillator and latched 3-state bus interface.
Features
* * * * * * * * Complete receiver in an 18-pin package. Excellent performance. CMOS, single 5 volt operation. Minimum board area. Central office quality. Low power consumption. Power-Down mode (HM9270D only). Inhibit-mode (HM9270D only).
Pin Configurations
HM9270C
IN+ IN GS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE IN+ IN GS
HM9270D
1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE
VREF IC* IC* OSC1 OSC2 VSS
VREF INH PWDN OSC1 OSC2 VSS
* Connect to VSS
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HM 9270C/D DTMF RECEIVER
Block Diagram (Figure 1)
INH
HIGH GROUP FILTER IN+ IN
DIGITAL ZERO CROSSING DETECTORS DETECTION
CODE CONVERTER AND
Q1 Q2 Q3 Q4
+ -
DIAL TONE FILTER
LOW GROUP FILTER
ALGORITHM
LATCH
GS
CHIP CHIP CHIP CHIP CLOCKS POWER BIAS REF
OSC2 BIAS CIRCUIT + STEERING LOGIC
OSC1
VDD V
SS
PWDN
VREF St/ GT
ESt
StD
TOE
Pin Description Pin
1 2 3
Sym.
IN+ INGS
Function
Non-Inverting input Connections to the front-end differential amplifier. Invering Input Gain select. Gives access to output of front-end differential amplifier for connection of feedback resistor. Reference voltage output,nominally VDD/2. May be used to bias the inputs at midrail (see application diagram). Inhibit (input) logic high inhibit the detection of 1633Hz internal built-in pull down resistor. (HM9270D only). Power down (input). Active high power down the device and inhibit the oscillator internal built-in pull down resistor. (HM9270D only). Clock Input Output Clock 3.579545 MHz crystal connected between these pins completes internal oscillator.
4
VREF INH
5
6
PWDN
7 8 9 10
OSC1 OSC2 VSS TOE
Negative power supply, normally connected to 0V. 3-state data output enable (input). Logic high enables the outputs Q1-Q4. Internal pull-up.
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HM 9270C/D DTMF RECEIVER
Pin
11 12 13 14 15
Sym.
Q1 Q2 Q3 Q4 StD
Function
3-state data outputs. When enabled by TOE, provide the code corresponding to the last valid tone-pair received (see code table).
Delayed steering output. Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below VTSt. Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Steering input/guard time output (bi-directional). A voltage greater than VTSt detected at St causes the device to register the detected tone-pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone-pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St (see truth table). Positive power supply, +5Volts.
16
ESt
17
St/GT
18
VDD
Absolute Maximum Ratings (Notes 1, 2 and 3) Parameters Min. Max. Units
Power Supply Voltage, VDD - VSS 6 V Voltage on any pin VSS - 0.3 VDD+ 0.3 V Current at any pin 10 mA o Operating temperature -40 +85 C o Storage temperature -65 +150 C Package power dissipation 500 mW Note 1. Absolute maximum ratings are those values beyond which damage to the device may occur. 2. Unless otherwise specified, all voltages are referenced to ground. 3. Power dissipation temperature derating: -12 mV/oC from 65oC to 85oC
DC Electrical Characteristics Parameter Description
SUPPLY: VDD Icc Po IS INPUTS: VIL VIH IIH/IIL Iso RIN VTSt Operating Supply Voltage Operating Supply Current Power Consumption Standby Current
Test Conditions
Min. Typ. Max. Units
4.75 5.25 7 35 100 V mA mW A
f=3.579MHz; VDD=5V PWDN pin = VDD
-
3.0 15 -
Low Level Input Voltage High Level Input Voltage Input Leakage Current Pull Up (Source) Current Input Signal Impedance Inputs 1,2 Steering Threshold Voltage
1.5 3.5 VIN=Vss or VDD TOE (Pin 10)=OV @ 1kHz 0.1 7.5 10 2.35 -315
V V uA uA M V
HM 9270C/D DTMF RECEIVER
Parameter OUTPUTS: VOL VOH IOL IOH VREF ROR
Description
Test Conditions No Load No Load VOUT=0.4V VOUT=4.6V No Load
Min.
Typ. 0.03 4.97 2.5 0.8
Max.
Units V V mA mA V K
Low Level Output Voltage High Level Output Voltage Output Low (Sink) Current Output High (Source) Current Output Voltage VREF Output Resistance
1.0 0.4 2.4
2.7 10
Operating Characteristics Gain Setting Amplifier
Parameter IIN RIN VOS PSRR CMRR AVOL fC VO CL RL VCM Description Input Leakage Current Input Resistance Input Offset Voltage Power Supply Rejection Common Mode Rejection DC Open Loop Voltage Gain Open Loop Unity Gain Bandwidth Output Voltage Swing Tolerable capacitive load(GS) Tolerable resistive load(GS) Common Mode Range Test Conditions VSS < VIN < VDD Min. Typ. Max. 100 10 25 60 60 65 1.5 4.5 100 50 3.0 Units nA M mV dB dB dB MHz VPP pF K VPP
1kHz -3.0V RL100K to VSS
No Load
Notes : 1.All voltages referenced to VDD unless otherwise noted. 2.VDD= 5.0V, VSS = 0V, TA = 25oC .
AC Characteristics
All voltages referenced to VSS unless otherwise noted. VDD=5.0V, VSS=0V, TA = 25OC, FCLK=3.579545 MNz, using test circuit of figure 2. Parameter Description Min. Typ. Max. Units Notes
SIGNAL COITIONS: Valid Input Signal level (each tone signal):MIN MAX +1 883 10 10
-40 7.75
dBm mVRMS dBm mVRMS dB dB Nom. Nom. dB dB
1,2,3,5,6,9,11 1,2,3,5,6,9,11 1,2,3,5,6,9,11 2,3,6,9,11
Twist Accept Limit: Positive Negative Freq. Deviation Accept Limit Freq. Deviation Reject Limit Third Tone Tolerance Noise Tolerance Dial Tone Tolerance
1.5%2 Hz 3.5% -16 -12 +18
2,3,5,9,11 2,3,5,11 2,3,4,5,9,10,11 2,3,4,5,7,9,10,11 2,3,4,5,8,9,10,11
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HM 9270C/D DTMF RECEIVER
Parameter
TIMING: tDP tDA tREC tREC tID tDO OUTPUTS: tPQ tPSED tQSED tPTE tPTD CLOCK: fCLK CLO
Description
Tone Present Detection Time Tone Absent Detection Time Tone Duration Accept Tone Duration Reject Interdigit Pause Accept Interdigit Pause Reject
Min. Typ. Max.
5 0.5 20 40 ms 14 4 16 8.5 40
Units
ms ms ms ms ms
Notes
Refer to Fig. 4
(User Adjustable) Refer to "Guard Time
20
Adjustment"
Propagation Delay (St to Q) Propagation Delay (St to StD) Output Data Set Up (Q to Std) Propagation ENABLE Delay (TOE to Q) DISABLE
8 12 4.5 50 300
11
60
s s s ns ns
TOE= VDD
RL=10k CL=50pf
Crystal/Clock Frequency Clock Output Capacitive (OSC2) Load
3.5759 3.5795
3.581 MHz 30 pf
Notes: 1.dBm = decibels above or below a reference power of 1mW into a 600 Ohm load. 2.Digit sequences consists of all 16 DTMF tones. 3.Tone duration = 40mS Tone pause = 40mS. 4.Nominal DTMF frequencies are used. 5.Both tones in the composite signal have an equal amplitude. 6.Tone pair is deviated by 1.5% 2Hz. 7.Bandwidth limited (3kHz) Gaussian Noise. 8.The precise dial tone frequencies are (350Hz and 440Hz) 2%. 9.For an error rate of less than 1 in 10,000. 10.Referenced to the lowest level frequency component in DTMF signal. 11.Added A 0.1f capacitor between V DD and VSS.
Function Description
HM9270C
5V
0.1f
100 NF 100 K 100 K
IN+ IN GS VREF IC IC 3.58 MHz OSC1 OSC2 VSS
VDD St/GT ESt StD Q4 Q3 Q2 Q1
TOE
100NF 300 K
FIGURE 2. SINGLE ENDED INPUT CONFIGURATION -5-
HM 9270C/D DTMF RECEIVER
HM9270D
5V
0.1f
100 NF
Vin
IN+ IN
VDD St/GT ESt StD Q4 Q3 Q2 Q1
TOE
100NF 300 K
100 K
GS 100 K VREF INH PWDN 3.58 MHz OSC1 OSC2 VSS
5V
FIGURE 3. SINGLE ENDED INPUT CONFIGURATION The HM9270C/D monolithic DTMF receiver offers small size, low power consumption and high performance. Its architecture consists of a bandsplit filter section, which separates the high and low tones of receiver pair, followed by a digital counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. FILTER SECTION Separation of the low-group and high-group tones is achieved by applying the dual tone signal to the inputs of two filters a sixth order for the high group and an eighth order for the low group. The bandwidths of which correspond to the bands enclosing the low-group and high-group tones (see Fig. 4). The filter section also in corporates notches at 350Hz and 440 Hz for exceptional dial-tone rejection. Each filter output is followed by a second-order switched-capacitor section which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals and noise; the outputs of the comparators provide full-rail logic swings at the frequencies of the incoming tones. Flow Fhigh KEY TOE Q4 Q3 Q2 697 1209 1 H 0 0 0 Decoder Section 697 1336 2 H 0 0 1 The decoder used digital counting techniques to 697 1477 3 H 0 0 1 determine the frequencies of the limited tones and to 770 1209 4 H 0 1 0 verify that they correspond to standard DTMF 770 1336 5 H 0 1 0 frequencies. A complex averaging algorithm(protects) 770 1477 6 H 0 1 1 against tone simulation by extraneous signals, such as 852 1209 7 H 0 1 1 voice, while providing tolerance to smalll frequency 852 1336 8 H 1 0 0 deviations and variations. This averaging algorithm has 852 1477 9 H 1 0 0 been developed to ensure an optimum combination of 941 1336 0 H 1 0 1 immunity to "talk-off" and tolerance to the presence of 941 1209 * H 1 0 1 interfering signals ("third tones") and noise. When the 941 1477 # H 1 1 0 detector recognizes the simultaneous presence of two 697 1633 A H 1 1 0 valid tones (referred to as "signal condition" in some 770 1633 B H 1 1 1 industry specifications), it raises the "early steering" 852 1633 C H 1 1 1 flag (ESt). Any subsequent loss of signal condition will 941 1633 D H 0 0 0 cause ESt to fall. ANY L Z Z Z L = LOGIC LOW , H = LOGIC HIGH, Z = HIGH IMPEDANCE FIGURE 4. LOGIC TABLE -6Q1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Z
HM 9270C/D DTMF RECEIVER
FIGURE 5. TIMING DIAGRAM
D
EVENTS
A
B t REC TONE # n t
DP
C INTERDIGIT PAUSE t ID
E
F TONE DROPOUT
G t DO
t REC
TONE #n+1 t DA
TONE#n+1
ESt
V Tst t GTP t
GTA
St/GT t DATA OUTPUTS Q1-Q4 StD OUTPUT t TOE t
PTE PTD PQ
DECODE TONE n-1
DECODED TONE#n t PS t D
HIGH IMPEDANCE
DECODED TONE # n + 1
A. Short tone bursts: detected. Tone duration is invalid. B. Tone #n is detected. Tone duration is valid. Decoded to outputs. C. End of tone #n is dectected and validated. D. 3 State outputs disabled (high impedance). E. Tone #n + 1 is detected. Tone duration is valid. De coded to outputs. F. Tristate outputs are enabled. Acceptable drop out of tone #n + 1 does not negister at outputs. G. End of tone #n + 1 is detected and validated. FIGURE 5. TIMING DIAGRAM STEERING CIRCUIT
0 10 20 30 40 50 60
Before registration of a decoded tone-pair, the receiver checks 70 for a valid signal duration (referred to as "character-recogni80 tion-condition"). This check is performed by an external RC time-constant driven by ESt. 1K 0 2K A logic high on ESt causes VC (see Fig. 5) to rise as the capacitor discharges. Provided signal-condition is maintained (ESt remains high) for the validation period (t GTP), Vc reaches the threshold (VTSt) of the steering logic to register the FIGURE 6. TYPICAL FILTER tone-pair, latching its corresponding 4-bit code (see Fig. 3) CHARACTERISTIC into the output latch. At this point, the GT output is activated and drives VC to VDD. GT continues to drive high as long as ESt remains high. Finally after a short delay to allow the output latch to settle, the "delayed-steering" output flag, StD, goes high, signaling that a recieved tone-pair has been registered. The contents of the output lacth are made available on the 4-bit output bus by raising the 3-state control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit paues between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions ("drop-out") too short to be considered a valid pause. The facility, together with the capability of selecting the steering time-constants externally, allows the designer to tailor performance to meet a wide variety of system requiremetns. -7-
HM 9270C/D DTMF RECEIVER
0.1f
C
V DD
V DD St/GT ESt R S tD VC
t
GTA =(RC) ln (
V DD V TST
)
t
GTP
=(RC) ln (
V DD ) V DD - V TST
FIGURE 7. BASIC STEERING CIRCUIT Guard Time Adjustment In many situations not requiring independent selection of receive and pause, the simple steering circuit of Fig. 7 is applicable. Component values are chosen according to the following formulae: tREC = tDP + tGTP tID = tDA + tGTA The value of tDP is a parameter of the device (see table) and tREC is the minimum signal duration to be recognized by the receiver. A value for C of 0.1 F is recommended for most applications, leaving R to be selected by the designer. For example, a suitable value of R for a tREC of 40mS would be 300k. Different steering arrangements may be used to select independently the guard-times for tone-present (tGTP) and tone-absent (tGTA). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and interdigital pause. Guard-time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. Increasing tREC improves talk-off performance, since it reduces the probability that tones simulated by speech will maintain signal condition for long enough to be registered. On the other hand, a relatively short tREC with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to drop - outs would be required. Design information for guard-time adjustment is shown in Fig. 8.
VDD C S t / GT R1 ES t
VDD VDD - VTST VDD tGTA=(R1 C) In ( ) VTST R1R2 Rp= R1+R2 tGTP=(Rp C) In ( )
V
DD
C S t / GT
R2
R1 ES t
VDD VDD - VTST VDD ) tGTA=(R1 C) In ( VTST R1R2 Rp= R1+R2 tGTP=(Rp C) In (
R2
)
a) Decreasing tGTP (tGTP < tGTA) b) Decreasing tGTP (tGTP > tGTA) FIGURE 8. GUARD TIME ADJUSTMENT -8-
HM 9270C/D DTMF RECEIVER
Input Configuration The input arrangement of the HM9270C/D provides a differential-input operational amplifier as well as a bias source (VREF ) which is used to bias the inputs at mid-rail. Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in Fig. 2 with the op-amp connected for unity gain and VREF biasing the input at 1/2VDD. Fig. 9 shows the differential configuration, which permits the adjustment of gain with the feedback resistor R5.
C1 R1 + C2 R4 GS HM9270C/D
R5
R3 R2 VREF
FIGURE 9. DIFFERENTIAL INPUT CONFIGURATION Power - down and inhibit mode A logic high applied to pin 6 (PWDN) will power the device to minimize the power consumption in a standby mode. It stops the oscillator and the functions of the filters. Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of 1633 Hz. The output code will remain the same as the previous detected code (see table 1). fLow 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 Fhigh Key 1209 1 1336 2 1477 3 1209 4 1336 5 1477 6 1209 7 1336 8 1477 9 1336 0 1209 * 1477 # 1633 A 1633 B 1633 C 1633 D ANY TOE Q4 H L H L H L H L H L H L H L H H H H H H H H H H H H H H H H H L L Z Q3 L L L H H H H L L L L H H H H L Z Q2 L H H L L H H L L H H L L H H L Z Q1 H L H L H L H L H L H L H L H L Z fLow 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 Fhigh Key 1209 1 1336 2 1477 3 1209 4 1336 5 1477 6 1209 7 1336 8 1477 9 1336 0 1209 * 1477 # 1633 A 1633 B 1633 C 1633 D ANY TOE Q4 Q3 Q2 Q1 H L L L H H L L H L H L L H H H L H L L H L H L H H L H H L H L H H H H H L L L H H L L H H H L H L H H L H H H H H L L H H PREVIOUS DATA H H L Z Z Z Z
Table 1: Truth table INH =VSS (Z: high impedance) INH=VDD
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HM 9270C/D DTMF RECEIVER SPECIAL PACKAGE PIN CONFIGURATIONS
HM9270DM
IN+ INGS VREF INH PWDN OSC1 OSC2 VSS NC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD St/GT EST StD Q4 Q3 Q2 Q1 TOE NC
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